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CXB1561Q-Y
s3R-IC for Optical Fiber Cimmunication Receiver
Description The CXB1561Q-Y achieves the 3R optical-fiber cimmunication receiver functions (Reshaping, Regenerating and Retiming) on a single chip using with a SAW filter. Features * 3R-IC with a built-in post-amplifier (SAW filter system) * Signal interruption alarm output * Data shutdown function for signal interruption * Timing phase can be fine adjusted * Delay length for edge detector (differentiator) can be selected * Single 5V power supply Absolute Maximum Ratings * Supply voltage VCC - VEE -0.3 to +7.0 * Operating case temperature -55 to +125 TC * Storage temperatureTstg -65 to +150 * Output current (surge current) Io 0 to 50 (100) * D/D input current IID -200 to +400 * SC/SC input current IIC -100 to +400 * S1/S2 input voltage VIS VCC to VEE + 1.2 Recommended Operating Conditions * Supply voltage VCC - VEE 5.0 0.5 * Operating case temperature TC -40 to +85 32 pin QFP (Ceramic)
Structure Bipolar silicon monolithic IC Applications * SONET: 622.08Mbps, 155.52Mbps * Fiber channel: 531.25Mbps, 265.625Mbp * Clock multiplication: X2, X4
V C C mA A A V
V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E93615B6Z
CXB1561Q-Y
Block Diagram
VEEDA
VCCDA
CA
CA
Q
24 VEEA D D CAP1 CAP1 S1 S2 VCCA 25 26 27 28
23
22
21
20
19
Q
18
VCCDI
Limit Amp
VCCAL
17 16 SC 15 SC VEEDB 14 VEEAL 13 SQ 12 SQ 11 VCCDB 10 VEEDB 9 SD VEEDB 8
Delay D-FF
delay2 delay1
29 30 31 32 1 2 3 4 5
ALARM peak hold peak hold
6
Differential
7
Post Amp
DOWN
-2-
CAP2
CAP3
VEED
VccD
VEE
UP
SD
CXB1561Q-Y
Pin Description Pin No. 1 2 Symbol VccD VEED Typical pin voltage DC 0V -5V
VCCA 1k
AC
Equivalent circuit
Description Positive power supply pin for digital block. Negative power supply pin for digital block. Resistor connection pins for alarm level setting. UP pin: When the resistance connection to this pin is increased, the alarm level becomes higher. DOWN pin: When the resistance connected to this pin is increased, the alarm level becomes lower. Capacitance connection pins for alarm block peak hold circuit. (Each pin incorporates a capacitance of approximately 10pF.) CAP2 pin: Peak hold capacitance connection pin for the post-amplifier signal output. CAP3 pin: Peak hold capacitance connection pin for the alarm level setting block. Negative power supply pin.
3
UP
-1.3V
100 3 200 4 200 100
4
DOWN
-1.3V
VEEA 0.8mA 0.8mA
5
6 VCCA
5
CAP2
-1.8V
80 80
6
CAP3
-1.8V
5A 20A
10p
10p
5A VEEA VCCD
7
VEE
-5V -0.9V to -1.7V
8
SD
8
Alarm output pins. Terminate these pins in 510 at VEE.
9
SD
-0.9V to -1.7V
9 VEED
10 11
VEEDB VCCDB
-5V 0V
Negative power supply pin for differential circuit. Positive power supply pin for differential circuit.
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CXB1561Q-Y
Pin No.
Symbol
Typical pin voltage DC AC -0.9V to -1.7V
Equivalent circuit
Description
VCCDB
12
SQ
13
Differential output pins.
13
SQ
-0.9V to -1.7V
12 510 VEED 510 VEEDB
14
VEEAL
-5V
VCCAL
Negative power supply pin for limiter amplifier.
15
SC
-1.3V
-0.9V to -1.7V
200 16 15 200 50 1k 100p 1k
Limiter amplifier input pins. Ensure that these inputs are AC-coupled.
16
SC
-1.3V
-0.9V to -1.7V
50 0.4mA 0.4mA VEEAL
17 18
VccAL VccDI
0V 0V
VCCDA
Positive power supply pin for limiter amplifier. Positive power supply pin for internal digital circuit.
19
Q
-0.9V to -1.7V
19
20
Q
-0.9V to -1.7V
20
Data signal output pins. Terminate these pins in 50 at VTT = -2V.
VEEDA
21
VccDA
0V
Positive power supply pin for output circuit.
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CXB1561Q-Y
Pin No.
Symbol
Typical pin voltage DC AC -0.9V to -1.7V
Equivalent circuit
VCCDA
Description
22
CA
--
22
Clock signal output pins. Terminate these pins in 50 at VTT = -2V
23
CA
--
-0.9V to -1.7V
23 VEEDA
24 25
VEEDA VEEA
-5V -5V -0.9V to -1.7V -0.9V to -1.7V
26 27 200 1k 10k100p 200 10k 200 28 29
Negative power supply pin for output circuit. Negative power supply pin for analog block.
VCCAL 200
26
D
-1.3V
27
D
-1.3V
Post-amplifier input pins. Ensure that these inputs are AC-coupled.
28
CAP1
1k 0.8mA
0.8mA
VEEA
29
CAP1
Capacitance connection pins to determine the high cut-off frequency for post-amplifier feedback.
VCCD
20k
30
S1
-2.0V
30 200 50k 0.1mA VEED
Delay switchover input pin for delay block. T = T (S1: High) - T (S1: open Low) = 134ps (typ. target)
VCCD
20k
31
S2
-2.0V
31 200 50k 0.1mA VEED
Pulse width switchover input pin for differential circuit. S2: open low For 622Mbps S2: High For 155Mbps
32
VccA
0V
Positive power supply pin for analog block.
-5-
CXB1561Q-Y
Electrical Characteristics * DC characteristics Item Supply current CA/CA, Q/Q High output voltage CA/CA, Q/Q Low output voltage SD/SD High output voltage SD/SD Low output voltage S1/S2 High input voltage S1/S2 Low input voltage S1/S2 High input current S1/S2 Low input current 1 VEE = -5V, Tc = 0 to 85C * AC characteristics Item Data rate D/D input resistance Symbol Da Db RINM Symbol IEE VOH-Vcc
(Vcc = 0V, VEE = -5V 10%, Tc = -40 to 85C) Conditions Termination: Rt = 50, VTT = -2V1 Termination: Rt = 50, VTT = -2V VOL-Vcc Termination: Rt = 50, VTT = -2V1 Termination: Rt = 50, VTT = -2V Termination: Rt = 510, to VEE1 Termination: Rt = 510, to VEE VOLa-Vcc VIH-Vcc VIL-Vcc IIH IIL -90 Termination: Rt = 510, to VEE1 Termination: Rt = 510, to VEE Min. -157 -1.03 -1.15 -1.81 -1.86 -1.08 -1.20 -1.90 -1.95 -1.17 -3.00 Typ. -110 Max. -74 -0.88 -0.88 -1.62 -1.60 -0.82 -0.83 -1.57 -1.55 0 -1.47 150 A V Unit mA
VOHa-Vcc
(Vcc = 0V, VEE = -5V 10%, VTT = -2V, Tc = -40 to 85C) Conditions S2: open low S2: High Min. 414.72 155.52 750 For single-end input, DC cut-off Internal signal: 400mV S2: open low S2: High Output, DC cut-off, 50 load 50 load, 20% to 80% 1000 45 525 1050 480 200 200 37.5 For single-end input, DC cut-off Internal signal: 400mV 1000 30 320 200 50 load, 20% to 80% 200 150 120 45 -6- 340 440 410 245 215 50 650 650 350 350 55 % ps 760 1625 670 300 300 50 1075 2150 850 420 400 62.5 Typ. 622.08 311.04 1000 1250 Max. Unit Mbps mVp-p dB ps mV ps mVp-p dB deg
D/D input identification max. voltage VmaxM Post Amp Gain SQ output pulse width SQ output amplitude SQ rise time SQ fall time SC/SC input resistance SC/SC input identification max voltage Limit Amp Gain Phase margin for the flip-flop block Q/Q rise time Q/Q fall time CA/CA rise time CA/CA fall time CA/CA output duty cycle GP d1 d2 VoB TrB TfB RinL VinL GL TrQ TfQ TrC TfC Du
CXB1561Q-Y
Item Identification maximum voltage amplitude of alarm level Hysteresis width SD/SD response assert time SD/SD response deassert time
Symbol VmaxA P Tas Tdas
Conditions D*single-phase input conversion 2 Low High2 High Low2
Min. 30 2
Typ.
Max.
Unit mVp-p
6
12 100
dB s
2.5
100
2 CAP2/CAP3 pin capacitance 470pF, V (UP pin) - V (DOWN pin) = 10mV, D input voltage = 130mVp-p
Electrical Characteristics Measurement Circuit For DC Characteristics
VTT 50
V V
50 50 50
V V
24 25 VD RD C1 26 C3
V
23
22
21
20
19
18
17 16
51 C6
Limit Amp
C4 15 Delay D-FF VEEDB 14 13 delay2 delay1
V
VSC
27 28 C2 29
Differential
Post Amp
12 VEEDB 11
V
VS1
A
30 31 32 1 2 3 4 5 6 7 ALARM peak hold peak hold
VS2
A
10
V
9 510 8 510
V
A
VEE
VUP VDOWN
C7
C8
-7-
CXB1561Q-Y
For AC Characteristics
Oscilloscope 50 input Z0 = 50
Z0 = 50 Z0 = 50
Z0 = 50
Z0 = 50
Z0 = 50
24 25 VD 470pF 26 470pF 27 28 0.033F VS1
A
23
22
21
20
19
18
17 100pF 16 100pF 15
Limit Amp
Delay D-FF VEEDB 14
VSC
1000pF 13 delay2 delay1
Differential
Post Amp
1000pF 12 VEEDB 11
29 30 31 32
VS2
A
ALARM peak hold peak hold
10 9 510
VCC
1
2
3
4
5
6
7
8
510
VEE
VUP VDOWN 470pF 470pF Oscilloscope High impedance input
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CXB1561Q-Y
Application Circuit
VTT 51 51 9 51 8 51
24 25 VD RD C1 26 1 27 RD C3 28 C2 29 30 31 32 1
A
23
22
21
20
19
18
17 16
51 C6
Limit Amp
C4 5 Delay D-FF 6 13 delay2 2 delay1 VEED B 14 1000pF 51 51 12 3 VEED 11 B 10 7 2 3 4 5 6 7 8 9 10 510 510 1000pF 15 4
ALARM peak hold peak hold
VEE
R5
R6
C7
C8
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
-9-
Differential
Post Amp
SAW
Timing Chart Sectional waveforms of the Application circuit
Alarm level set up by R5/R6
1
Input (D)
2
Post-amplifier output
3
Differentiator output (SQ)
td
4
SAW output (SC)
5
Limiter amplifier output
6
Delay block output
- 10 -
Tsa
7
Shutdown signal
8
Data output (Q)
9
Clock output (CA) Tdas
10
Alarm output (SD)
Alarm Block Logic SD Low level High level -- Fixed at High level Q
Optical signal input status
SD
Signal input
High level
Signal interruption
Low level
CXB1561Q-Y
Only the data (Q. Q), not clock, is shut down for signal interruption.
CXB1561Q-Y
Description of Operation 1. Overall operations The structure of optical-fiber communication receiver system is shown in Fig. 1. The CXB1561Q-Y performs the 3R operations indicated below.
* Photodiode .........Converts a data optical signal to a current signal. * Pre Amp..............Converts a data current signal to a voltage signal (however, the voltage level is feeble). * 3R .......................1) Amplifies a feeble data voltage signal (Reshaping). 2) Outputs a data signal in sync with a clock signal (Retiming). 3) Outputs both data and clock signals as ECL level signals (Regenerating).
Optical signal Vcc
Pre Amp Current signal Voltage signal
3R
Data signal
Clock signal
Fig. 1. Optical fiber communication receiver system clock The signal flow of the CXB1561Q-Y, including the SAW filter, is as shown in Fig. 2. First, the feeble signal output of the pre-amplifier enters the post-amplifier and is amplified to an IC internal logic level. The amplified signal is then divided into the clock and data sides shown below. The clock side derives a clock signal from a data signal. First, the post-amplifier signal enters the differentiator, which generates a pulse output having an uniform width at the signal rise and fall times. This output pulse enters the SAW filter, which generates resonance at regular intervals and outputs a SIN wave having a resonance frequency. This signal output then enters the limiter amplifier and is amplified to an IC internal logic level. This amplified signal is used as the DFF block clock signal. In the data side, on the other hand, the post-amplifier signal enters the delay section, where the signal is delayed to accomplish data/clock synchronization at the D-FF block. The signals separated into the clock and data sides are therefore synchronized with each other at the D-FF block and output to the outside.
Clock side Differentiator Feeble signal (from pre-amplifier) SAW Limit Amplifier Data output
Post-amplifier
D-FF
Delay Data side
Clock signal
Fig. 2. Signal flow
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CXB1561Q-Y
2. Delay length selection for edge detector (differentiator) (S2 pin operations) The larger the resonance frequency (SAW filter) component in the input signal, the greater the SAW filter output. Therefore, the CXB1561Q-Y is designed to offer differing differentiator pulse widths in the 622.08Mbps and 155.52Mbps of the SONET. The pulse width varies as follows according to the S2 pin input. S2: open Low S2: High For 622.08Mbps, 531.25Mbps For 155.52Mbps, 265.625Mbps
3. Timing phase fine adjustment (S1 pin operations) As explained under overall operations, the data signal delay is adjusted by the delay block to synchronize the clock and data signals at the D-FF block. However, as the clock signal is output to the outside when it passes through the SAW filter, the clock delay varies with the SAW filter type and on-board wiring length. To compensate for such a clock external delay variations more or less, the delay provided by the data delay section can be varied by switching S1 pin input. The delay change T is set up as follows. T = T (S1: open Low) - T (S1: High) = 134ps (design target value) The above indicates that the delay provided by the data delay block is T greater when S1 is open Low than when S1 is High.
4. Alarm output and data shutdown functions When the input signal level is lower than the alarm setting level, the CXB1561Q-Y generates an alarm signal and forcibly places the data output on a High level. For alarm level identification, a comparator having a hysteresis function is used to prevent misoperations of alarm output. The hysteresis width is designed so that the gain is always maintained constant (design target value: 6dB) without regard to the alarm setting level. The alarm level setting is determined by the voltage difference between Pins 3 (UP) and 4 (DOWN). Therefore, a desired voltage should be generated between the UP and DOWN pins and that the UP pin voltage is higher than the DOWN pin voltage.
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CXB1561Q-Y
Notes of Operation 1. Post-amplifier block In the post-amplifier block, the DC bias is automatically fed back by capacitors C1 and C2 as shown in Fig. 3. So, input with the DC cut-off. External capacitor C1 and IC internal resistor R1 determine the low input cut-off frequency f2 for post-amplifier, and external capacitor C2 and IC internal resistor R2 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the lower frequency of the amplifier gain characteristics depending on the f1/f2 combination, set the C1 and C2 values so as to avoid the occurrence of peaking characteristics. The R1 and R2 target values and C1 and C2 typical values are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 27 to capacitor C3 that has the same capacitance as capacitor C1. As this circuit is designed for mark density 1/2.,it is not recommended to use for mark density substantially different from 1/2. R1 (internal) 1k f2 340kHz C1 (external) 470pF R2 (internal) 10k f1 480Hz C2 (external) 0.033uF
26 C1 27 C3 R1 6 C2 5 R2 R1 R2 To IC interior
Fig. 3.
Feedback gain frequency response characteristic
Amplifier gain frequency response characteristic
Gain
f1
f2 Frequency
Fig. 4.
- 13 -
CXB1561Q-Y
2. Limiter amplifier block In the limiter amplifier block, the DC bias is automatically fed back by capacitor C4 and IC internal capacitor C5 as shown in Fig. 5. So, input with the DC cut-off. As is the case with the post-amplifier, external capacitor C4 and IC internal resistor R3 determine the low input cut-off frequency f2 of limiter amplifier. Further, IC internal capacitor C5 and IC internal resistor R4 determine the high cut-off frequency f1 for DC bias feedback. Since peaking characteristics may occur in the lower frequency of the amplifier gain characteristics depending on the f1/f2 combination, set the C4 value so as to avoid the occurrence of peaking characteristics. The R3, R4, and C5 target values and C4 typical value are as indicated below. When a single-ended input is used, provide AC grounding by connecting Pin 16 to capacitor C6 that has the same capacitance as capacitor C4. R3 (internal) 50 f2 32MHz C4 (external) 100pF R4 (internal) 1k f1 1.6MHz C5 (internal) 100pF
R4 C5 R4 R3 R3
16 To IC interior 15 C4 C6
Fig. 5.
- 14 -
CXB1561Q-Y
3. Alarm block As shown in Fig. 6, the alarm block requires alarm level setting external resistors R5 and R6 and peak hold capacitors C7 and C8. When the resistance value provided for resistor R5 is increased, the alarm setting level rises. When the resistance value provided for resistor R6 is increased, the alarm setting level lowers. However, the voltage of Pin 3 should be higher than the voltage of Pin 4. For the alarm level setting, see Fig. 7. In the relationship between the alarm setting level and hysteresis width, the hysteresis width maintains a constant gain (design target value: 6dB) as shown in Fig. 8. External capacitors C7 and C8 are used for input signal and alarm level peak hold capacitance. The C7 and C8 capacitance values should be set so as to obtain desired assert time and deassert time settings for the alarm signal. The additional resistances R10 and R11 make deassert time smaller. The R5, R6, C7, and C8 typical values are as indicated below. (A capacitance of approximately 10pF is built in Pins 5 and 6 respectively.)
R5 5k + R6 5k C7, 8 470pF
From MAIN AMP
peak hold
SD SD peak hold
10p VccA 3 R5 VEE 4 R6 VEE 5 6
10p VccA
C7
R10
C8
R11
Vcc VEE
Vcc VEE
Fig. 6.
16 14 12 VAS
VAS, VDAS (mVp-p)
VccA The values of R7, R8, and R9 are typical R7 1k R8 IC interior 3 IC exterior RU VEE RD 5k 4 100 R9 100
VDAS 10 8 6 4
VEE 2 0 5.0
5.2 RU (k)
5.4
5.6
Fig. 7. - 15 -
CXB1561Q-Y
SD output
High level VDAS Deassert level VAS Assert level
Low level
VDAS Small 3dB 3dB
VAS Great
Alarm setting input level Hysteresis Input electric signal amplitude
Fig. 8.
4. SAW peripheral board design In the signal flow from the differentiator through the SAW filter to the limiter amplifier, the signal is output to the outside at the SAW filter. To assure proper timing in the IC, therefore, the board wiring length must be appropriately designed. For the data and clock timing adjustment at the D-FF in the IC, the Typ. state position must conform to Fig. 9 because the D-FF phase margin is the greatest when the clock is positioned at the center of data. Further, the Min. state must comply with the D-FF setup time, and the Max. state must conform to the D-FF hold time. Since the clock signal occurs at regular intervals, synchronization must be accomplished at least at a certain integer multiple of the clock period. The above timing setup is derived from the equation below. The board wiring must therefore be designed to satisfy the equation.
- 16 -
CXB1561Q-Y
T = T (SAW filter delay time) + T (wiring delay time) {+ T (delay time for the IC which amplifies the SAW filter output when it is feeble)} (1) Typical value Construction shown in Fig. 10-a): T(typ.) = (n + 3/4) Tsaw - Tsdc (typ.) Construction shown in Fig. 10-b): T(typ.) = (n + 1/4) Tsaw - Tsdc (typ.) Minimum value T (min.) > T (typ.) + Tsff - 1/2 Tsaw + (Tsdc (typ.) - Tsdc (min.)) Maximum value T (max.) < T (typ.) - Thff + 1/2 Tsaw + (Tsdc (typ.) - Tsdc (max.))
(2) (3)
IC exterior IC interior Clock side Differentiator SAW Limiter Amplifier
2
From Post-amplifier
D-FF
Delay Data side 1
Data minimum pulse width TW
1
D-FF section data signal
Tw/2 Tsff Thff
2
D-FF section clock signal
Min.
Typ.
Max.
Fig. 9. D-FF timing
16
16
15
15
13 VEE 12 IC interior IC exterior
SAW
13 VEE 12 IC interior IC exterior
Fig. 10-a) - 17 -
Fig. 10-b)
SAW
CXB1561Q-Y
For the constants in the equation on the preceding page, see the table below. n = integer (0,1,2, * * *) Tsaw = SAW resonance frequency cycle 622.08Mbps Tsdc = Tsdc1 155.52Mbps Tsdc = Tsdc2 S2 pin: open Low T'sdc = Tsdc S2 pin: High T'sdc = Tsdc - T (Vcc = 0V, VEE = -5V 10%, Tc = 0 to 85C) Item Time difference for timing Variable delay time D-FF setup time D-FF hold time 622.08Mbps 155.52Mbps Symbol Tsdc1 Tsdc2 T Tsff Thff Min. 613 822 100 70 100 Typ. 747 1050 134 Max. 929 1549 163 ps Unit
When, for instance, the standard board wiring length is calculated for a data rate of 622Mbps, the following result is obtained. Tsaw = 1607.5ps Assuming the absolute phase of SAW filter = -10deg; Board wiring delay time 5.85ps/mm Construction Fig. 10-a) n=0 Under the above conditions, the following results. T (typ.) = (n+3/4) Tsaw - Tsdc (typ.) = (0 + 3/4) 1607.5 - 747 = 458.6ps T wiring length (typ.) = T (typ.) - TSAW filter = 458.6 - 1607.5 (10/360) = 413.9ps Wiring length (typ.) = T wiring length (typ)/(board wiring delay time) = 413.9/5.85 = 70.8mm
5. Order of power ON The CXB1561Q-Y has a number of power supplies. Note that the IC may break down if the following powerON order is not observed (no problem occurs when all the power supplies are turned ON simultaneously). (1) When all Vcc power supplies are turned ON first (The VCCA, VCCAL, VCCD, VCCDA, and VCCDB may be turned in any order.) Turn ON the VEE power supplies in any order. (2) When all VEE power supplies are turned ON first (The VEE, VEEA, VEEAL, VEED, VEEDA, and VEEDB may be turned in any order.) Turn ON the VCCAL, VCCDA, and VccDB (in any order) the VCCD VCCA.
- 18 -
CXB1561Q-Y
6. Differential Output Waveform The DC cut-off capacitance is connected between the differential output block and SAW filter as shown in Fig. 11 so that the waveforms are varied according to the ratio of the High level and Low level for the output waveform as shown in Fig. 12. So, note that the waveforms are different for SQ and SQ.
Differential output block A1 12 1000pF 13 A2 1000pF B2 VEE 50 50 B1 SAW
Fig. 11.
A1
A2 B1 B2
The High level for the SQ output pulse close to 50% A1 A2 B1 B2
The High level for the SQ output pulse close to 25%
Fig. 12.
- 19 -
CXB1561Q-Y
7. Evaluation Board Saw peripheral board design is important for system performance. Fig.13 shows Evaluation board for 622.08Mbps and the characteristics of the test circuit (Fig.14) is shown in Fig.15 to 18.
front back
VEE
VTT
VCC
SD
SD D
D
Q
Q
CA
CA
Fig. 13. Evaluation board pattern
Error Det Clock Data
Clock PPG Data PPG: Pulse Pattern Generator CA Z = 50 D CXB1561Q-Y Evaluation Board Q Q 51 Vtt Z = 50 Z = 50
CA 51 Vcc = +2V, Vee = -3V, Vtt = GND Vtt
Oscilloscope
Fig. 14. Measurement Circut - 20 -
CXB1561Q-Y
10-4 10-5 10-6 VEE = -5.0V Tc = 27C DIN = 622.08Mbps pattern: PRBS 223 - 1
Err Ratio
10-7 10-8 10-9 10-10 10-11 3 3.5 4 DIN (mVp-p) 4.5 5
Fig. 15. Error rate vs. Input signal (mark density 1/2, pattern 2N23-1, Tc = 27C)
50 Tr Tf 40
30
Jitter (ps)
20
10
0 1 10 DIN (mVp-p) 100 1000
Fig. 16. Clock jitter vs. Input signal (mark density 1/2, pattern 2N23-1, Tc = 27C)
- 21 -
CXB1561Q-Y
Fig. 17. jitter transfer (mark density 1/2, pattern 2N23-1, input voltage = 6mVp-p, Tc = 27C)
Fig. 18. jitter tolerance (mark density 1/2, pattern 2N23-1, input voltage = 6mVp-p, Tc = 27C)
- 22 -
CXB1561Q-Y
Package Outline
Unit: mm
32PIN QFP (CERAMIC)
14.73 0.3 24 17
4.92 MAX
0.15 0 .05
25
16
32
9
10.63 MAX
0.76
1 1.016
8
0.635 0.125
0.48 0.1 0 to 10
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-32C-L01 XQFP023-G-0000-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT CERAMIC TIN PLATING 42 ALLOY 0.3g
- 23 -
(0.825)

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